1. Field of the Invention
The present invention relates to a voltage adjusting circuit, and in particular, to a voltage adjusting circuit capable of stabilizing a voltage used as a cell plate voltage and a bit line precharge voltage for a dynamic random access memory (DRAM).
2. Background of the Related Art
In the related art, a half VCC voltage is used as a cell plate voltage V.sub.CP for a capacitor electrode to determine a quantity of electric charge of a signal, or as a bit line precharge voltage V.sub.BLP to determine a standard of signal detection. Accordingly, a half VCC generating circuit must rapidly respond to variations of a power supply voltage VCC and a load to maintain precision of the half VCC voltage.
FIG. 1 illustrates a block diagram of a related art half VCC generating circuit 100 that generates the bit line precharge voltage V.sub.BLP and the cell plate voltage V.sub.CP in accordance with a bit line precharge signal BLP.
FIG. 2 illustrates a first example of the related art half VCC generating circuit 100 consisting of first and second resistors R1, R2 and having an output voltage Vout represented by: EQU Vout=(R1/(R1+R2))*VCC. (1)
When the first resistor R1 and the second resistor R2 have substantially equal resistances, the power supply voltage VCC is divided equally by the first and second resistors R1, R2. Thus, the output voltage Vout becomes a half VCC voltage. The first example of the related art half VCC generating circuit 100 includes only the first and second resistors R1, R2, and is thus quite simple.
However, the first related art example has various disadvantages. For example, the related art first example circuit consumes much current.
FIG. 3 illustrates a second example of the related art half VCC generating circuit 100, having a bias circuit 10 that reduces current consumption and a push-pull output circuit 11 that enhances a driving force. The bias circuit 10 includes first and second transistors QN1, QP1 and first and second resistors R1, R2. The first transistor QN1 is of a diode NMOS type, and has a first electrode and a control electrode commonly connected to the first resistor R1 at a first node N1. The first transistor QN1 has a second electrode commonly connected to a first electrode and a control electrode of the second transistor QP1 at a second node N2, wherein the second transistor is of a diode PMOS type. A second electrode and the control electrode of the second transistor QP1 are commonly connected to the second resistor R2 at a third node N3. The first resistor R1 is connected between the first node N1 and the power supply voltage VCC, and the second resistor R2 is connected between the third node N3 and the ground VSS.
The push-pull circuit 11 includes a third NMOS transistor QN2 and a fourth PMOS transistor QP2. The third transistor QN2 has a first electrode connected to the power supply voltage VCC, a control electrode connected to the first node N1, and a second electrode commonly connected to the output voltage Vout and a first electrode of the fourth transistor QP2. The fourth transistor QP2 also has a control electrode connected to the third node N3 and a second electrode connected to the ground VSS.
If the resistances of the first and second resistors R1, R2 are sufficiently large in the bias circuit 10, a voltage of the second node N2 becomes the half VCC voltage, as described above. When threshold voltages of the first through fourth transistors QN1, QP1, QN2, QP2 are equally set at Vt, voltages of the first and third nodes N1, N3 are equal to (VCC/2)+Vt and (VCC/2)-Vt, respectively. As a result, a stable half VCC voltage is generated as the output voltage Vout. A gate-source voltage V.sub.GS of the third and fourth transistors QN2, QP2 in the push-pull output circuit 11 is also set at Vt, and thus, the third transistor QN2 and the fourth transistor QP2 are at a state just before being fully transited to the "ON" position, and a through current flows therein.
Accordingly, when the output voltage Vout is varied from the half VCC voltage, one of the third and fourth transistors QN2, QP2 is transited to the "ON" position, and the other is fully transited to the "OFF" position, to rapidly restrict variation of the half VCC voltage. Since N-well bias voltages of the second and fourth transistors QP1, QP2 are a half VCC voltage and a full VCC voltage, respectively, the fourth transistor QP2 receives more back gate effects than the second transistor QP1, and thus, a threshold voltage Vtp2 of the fourth transistor QP2 becomes greater than a threshold voltage Vtp1 of the second transistor QP1. As a result, when the output voltage Vout maintains a half VCC level, the second transistor QP2 is always transited to the "ON" position, and thus the through current does not flow in the push-pull output circuit 11.
Even if the third transistor QN2 and the fourth transistor QP2 are sufficiently increased in size to have a large load capacity, the consumption of power at the push-pull output circuit 11 is not increased. In addition, the current flowing in the bias circuit 10 can be reduced by increasing the values of the first and second resistors R1, R2.
However, the related art half VCC generating circuit has various problems and disadvantages. The cell plate voltage V.sub.CP depends on the VCC voltage, especially at a low voltage. Thus, the transient property of the related art circuit can result in various problems. For example, an absolute value difference of the threshold voltages of the NMOS type transistor and the PMOS the transistor becomes a setting error of the half VCC voltage generating circuit. When the NMOS transistor and PMOS transistor each have a process error of .+-.0.1V, respectively, the absolute value of the error of the half VCC voltage generating circuit equals 0.2V. Further, if the external power supply voltage is decreased, the relative error increases.
In addition, when a capacitance of the cell plate electrode or the bit line is increased four times in accordance with a generation of a dynamic random access memory DRAM, the driving capacity of the half VCC voltage generating circuit does not improve significantly, thereby worsening a transient response property of the half VCC generating circuit. A significant amount of time is thus required to obtain the stable half VCC voltage when the power supply voltage is applied. Furthermore, the half VCC generating circuit cannot rapidly respond to a sharp variation of the load or a VCC variation during operation of the DRAM.
FIG. 4 graphically illustrates a variation of the half VCC voltage according to the load variation in an active mode and a standby mode that results in various problems and disadvantages. The half voltage outputted from the half VCC voltage generating circuit 100 maintains a constant level at an initial operation, but decreases due to the current consumption in the active mode, including a read/write operation and a sense amp operation. If the half VCC voltage becomes lower than .DELTA.V, a defect may occur in a cell data.
Additionally, the half VCC voltage cannot maintain a predetermined level and causes voltage bouncing when the standby mode (i.e., a refresh operation) has a load. This phenomenon often takes place during an auto refresh operation, thus influencing the DRAM operation.